Oliver Stannard d414c99b9c [AArch64] Fix halfword load merging for big-endian targets ...

For big-endian targets, when we merge two halfword loads into a word load, the
order of the halfwords in the loaded value is reversed compared to
little-endian, so the load-store optimiser needs to swap the destination
registers.

This does not affect merging of two word loads, as we use ldp, which treats the
memory as two separate 32-bit words.

llvm-svn: 252597

2015-11-10 11:04:18 +00:00

47 KiB

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