Alex Bradbury 8971842f43 [RISCV] Initial codegen support for ALU operations ...

This adds the minimum necessary to support codegen for simple ALU operations
on RV32. Prolog and epilog insertion, support for memory operations etc etc 
follow in future patches.

Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is 
reviewed and lands.

Differential Revision: https://reviews.llvm.org/D29933

llvm-svn: 316188

2017-10-19 21:37:38 +00:00

1.6 KiB

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