Cyrill Leutwiler bd32aaa8c9 [RISCV] Support rv{32, 64}e in the compiler builtins (#88252) ...

Register spills (save/restore) in RISC-V embedded work differently
because there are less registers and different stack alignment.

[GCC equivalent
](https://github.com/gcc-mirror/gcc/blob/master/libgcc/config/riscv/save-restore.S#L298C16-L336)

Follow up from #76777.

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Signed-off-by: xermicus <cyrill@parity.io>

2024-04-11 13:11:51 +08:00

..

fp_mode.c

…

int_mul_impl.inc

…

muldi3.S

…

mulsi3.S

…

restore.S

[RISCV] Support rv{32, 64}e in the compiler builtins (#88252)

2024-04-11 13:11:51 +08:00

save.S

[RISCV] Support rv{32, 64}e in the compiler builtins (#88252)

2024-04-11 13:11:51 +08:00