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Author SHA1 Message Date
Shilei Tian
658d283e6c [AMDGPU] Rewrite getVregSrcForVT with !cond 2024-02-15 20:05:13 -05:00

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@@ -1528,15 +1528,14 @@ class getSOPSrcForVT<ValueType VT> {
// Returns the vreg register class to use for source operand given VT
class getVregSrcForVT<ValueType VT, bit IsTrue16 = 0, bit IsFake16 = 0> {
RegisterOperand ret =
!if (!eq(VT.Size, 128), RegisterOperand<VReg_128>,
!if (!eq(VT.Size, 96), RegisterOperand<VReg_96>,
!if (!eq(VT.Size, 64), RegisterOperand<VReg_64>,
!if (!eq(VT.Size, 48), RegisterOperand<VReg_64>,
!if (!eq(VT.Size, 16),
!if (IsTrue16,
!if (IsFake16, VGPRSrc_32_Lo128, VGPRSrc_16_Lo128),
RegisterOperand<VGPR_32>),
RegisterOperand<VGPR_32>)))));
!cond(!eq(VT.Size, 128) : RegisterOperand<VReg_128>,
!eq(VT.Size, 96) : RegisterOperand<VReg_96>,
!eq(VT.Size, 64) : RegisterOperand<VReg_64>,
!eq(VT.Size, 48) : RegisterOperand<VReg_64>,
!eq(VT.Size, 16) : !if(IsTrue16,
!if(IsFake16, VGPRSrc_32_Lo128, VGPRSrc_16_Lo128),
RegisterOperand<VGPR_32>),
1 : RegisterOperand<VGPR_32>);
}
class getSDWASrcForVT <ValueType VT> {