Files
llvm-project/llvm/test/CodeGen/PowerPC/tls.ll
Matthias Braun e2d2ce9ff1 PowerPC: Do not use llc -march in tests.
`llc -march` is problematic because it only switches the target
architecture, but leaves the operating system unchanged. This
occasionally leads to indeterministic tests because the OS from
LLVM_DEFAULT_TARGET_TRIPLE is used.

However we can simply always use `llc -mtriple` instead. This changes
all the tests to do this to avoid people using -march when they copy and
paste parts of tests.

This patch:
- Removes -march if the .ll file already has a matching `target triple`
  directive or -mtriple argument.
- In all other cases changes -march=ppc32/-march=ppc64 to
  -mtriple=ppc32--/-mtriple=ppc64--

See also the discussion in https://reviews.llvm.org/D35287

llvm-svn: 309754
2017-08-01 22:20:41 +00:00

47 lines
1.6 KiB
LLVM

; RUN: llc -relocation-model=static -verify-machineinstrs -O0 < %s -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s
; RUN: llc -relocation-model=static -verify-machineinstrs -O1 < %s -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s
; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=ppc32-- -mcpu=ppc | FileCheck -check-prefix=OPT0-PPC32 %s
target triple = "powerpc64-unknown-linux-gnu"
@a = thread_local global i32 0, align 4
;OPT0-LABEL: localexec:
;OPT1-LABEL: localexec:
define i32 @localexec() nounwind {
entry:
;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha
;OPT0-NEXT: addi [[REG1]], [[REG1]], a@tprel@l
;OPT0-NEXT: li [[REG2:[0-9]+]], 42
;OPT0: stw [[REG2]], 0([[REG1]])
;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha
;OPT1-NEXT: li [[REG2:[0-9]+]], 42
;OPT1-NEXT: stw [[REG2]], a@tprel@l([[REG1]])
store i32 42, i32* @a, align 4
ret i32 0
}
; Test correct assembly code generation for thread-local storage
; using the initial-exec model.
@a2 = external thread_local global i32
define signext i32 @main2() nounwind {
entry:
%retval = alloca i32, align 4
store i32 0, i32* %retval
%0 = load i32, i32* @a2, align 4
ret i32 %0
}
; OPT1-LABEL: main2:
; OPT1: addis [[REG1:[0-9]+]], 2, a2@got@tprel@ha
; OPT1: ld [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]])
; OPT1: add {{[0-9]+}}, [[REG2]], a2@tls
;OPT0-PPC32-LABEL: main2:
;OPT0-PPC32: li [[REG1:[0-9]+]], _GLOBAL_OFFSET_TABLE_@l
;OPT0-PPC32: addis [[REG1]], [[REG1]], _GLOBAL_OFFSET_TABLE_@ha
;OPT0-PPC32: lwz [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]])
;OPT0-PPC32: add 3, [[REG2]], a2@tls