550148b2f6
div/rem instructions in basic blocks that require predication currently prevent vectorization. This patch extends the existing mechanism for predicating stores to handle other instructions and leverages it to predicate divs and rems. Differential Revision: https://reviews.llvm.org/D22918 llvm-svn: 279620
91 lines
3.8 KiB
LLVM
91 lines
3.8 KiB
LLVM
; RUN: opt -S -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -verify-loop-info -simplifycfg < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; Test no-predication of instructions that are provably safe, e.g. dividing by
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; a non-zero constant.
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define void @test(i32* nocapture %asd, i32* nocapture %aud,
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i32* nocapture %asr, i32* nocapture %aur,
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i32* nocapture %asd0, i32* nocapture %aud0,
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i32* nocapture %asr0, i32* nocapture %aur0
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) {
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entry:
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br label %for.body
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for.cond.cleanup: ; preds = %if.end
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ret void
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; CHECK-LABEL: test
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; CHECK: vector.body:
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; CHECK: %{{.*}} = sdiv <2 x i32> %{{.*}}, <i32 11, i32 11>
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; CHECK: %{{.*}} = udiv <2 x i32> %{{.*}}, <i32 13, i32 13>
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; CHECK: %{{.*}} = srem <2 x i32> %{{.*}}, <i32 17, i32 17>
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; CHECK: %{{.*}} = urem <2 x i32> %{{.*}}, <i32 19, i32 19>
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; CHECK-NOT: %{{.*}} = sdiv <2 x i32> %{{.*}}, <i32 0, i32 0>
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; CHECK-NOT: %{{.*}} = udiv <2 x i32> %{{.*}}, <i32 0, i32 0>
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; CHECK-NOT: %{{.*}} = srem <2 x i32> %{{.*}}, <i32 0, i32 0>
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; CHECK-NOT: %{{.*}} = urem <2 x i32> %{{.*}}, <i32 0, i32 0>
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for.body: ; preds = %if.end, %entry
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ]
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%isd = getelementptr inbounds i32, i32* %asd, i64 %indvars.iv
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%iud = getelementptr inbounds i32, i32* %aud, i64 %indvars.iv
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%isr = getelementptr inbounds i32, i32* %asr, i64 %indvars.iv
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%iur = getelementptr inbounds i32, i32* %aur, i64 %indvars.iv
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%lsd = load i32, i32* %isd, align 4
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%lud = load i32, i32* %iud, align 4
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%lsr = load i32, i32* %isr, align 4
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%lur = load i32, i32* %iur, align 4
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%psd = add nsw i32 %lsd, 23
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%pud = add nsw i32 %lud, 24
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%psr = add nsw i32 %lsr, 25
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%pur = add nsw i32 %lur, 26
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%isd0 = getelementptr inbounds i32, i32* %asd0, i64 %indvars.iv
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%iud0 = getelementptr inbounds i32, i32* %aud0, i64 %indvars.iv
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%isr0 = getelementptr inbounds i32, i32* %asr0, i64 %indvars.iv
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%iur0 = getelementptr inbounds i32, i32* %aur0, i64 %indvars.iv
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%lsd0 = load i32, i32* %isd0, align 4
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%lud0 = load i32, i32* %iud0, align 4
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%lsr0 = load i32, i32* %isr0, align 4
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%lur0 = load i32, i32* %iur0, align 4
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%psd0 = add nsw i32 %lsd, 27
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%pud0 = add nsw i32 %lud, 28
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%psr0 = add nsw i32 %lsr, 29
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%pur0 = add nsw i32 %lur, 30
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%cmp1 = icmp slt i32 %lsd, 100
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %for.body
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%rsd = sdiv i32 %psd, 11
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%rud = udiv i32 %pud, 13
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%rsr = srem i32 %psr, 17
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%rur = urem i32 %pur, 19
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%rsd0 = sdiv i32 %psd0, 0
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%rud0 = udiv i32 %pud0, 0
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%rsr0 = srem i32 %psr0, 0
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%rur0 = urem i32 %pur0, 0
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br label %if.end
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if.end: ; preds = %if.then, %for.body
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%ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %for.body ]
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%yud.0 = phi i32 [ %rud, %if.then ], [ %pud, %for.body ]
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%ysr.0 = phi i32 [ %rsr, %if.then ], [ %psr, %for.body ]
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%yur.0 = phi i32 [ %rur, %if.then ], [ %pur, %for.body ]
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%ysd0.0 = phi i32 [ %rsd0, %if.then ], [ %psd0, %for.body ]
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%yud0.0 = phi i32 [ %rud0, %if.then ], [ %pud0, %for.body ]
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%ysr0.0 = phi i32 [ %rsr0, %if.then ], [ %psr0, %for.body ]
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%yur0.0 = phi i32 [ %rur0, %if.then ], [ %pur0, %for.body ]
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store i32 %ysd.0, i32* %isd, align 4
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store i32 %yud.0, i32* %iud, align 4
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store i32 %ysr.0, i32* %isr, align 4
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store i32 %yur.0, i32* %iur, align 4
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store i32 %ysd0.0, i32* %isd0, align 4
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store i32 %yud0.0, i32* %iud0, align 4
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store i32 %ysr0.0, i32* %isr0, align 4
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store i32 %yur0.0, i32* %iur0, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 128
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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