79997a24d7
For instructions in uniform set, they will not have vector versions so add them to VecValuesToIgnore. For induction vars, those only used in uniform instructions or consecutive ptrs instructions have already been added to VecValuesToIgnore above. For those induction vars which are only used in uniform instructions or non-consecutive/non-gather scatter ptr instructions, the related phi and update will also be added into VecValuesToIgnore set. The change will make the vector RegUsages estimation less conservative. Differential Revision: https://reviews.llvm.org/D20474 The recommit fixed the testcase global_alias.ll. llvm-svn: 275936
140 lines
5.2 KiB
LLVM
140 lines
5.2 KiB
LLVM
; RUN: opt < %s -debug-only=loop-vectorize -loop-vectorize -vectorizer-maximize-bandwidth -O2 -mtriple=x86_64-unknown-linux -S 2>&1 | FileCheck %s
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; RUN: opt < %s -debug-only=loop-vectorize -loop-vectorize -vectorizer-maximize-bandwidth -O2 -mtriple=x86_64-unknown-linux -mattr=+avx512f -S 2>&1 | FileCheck %s --check-prefix=AVX512F
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; REQUIRES: asserts
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@a = global [1024 x i8] zeroinitializer, align 16
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@b = global [1024 x i8] zeroinitializer, align 16
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define i32 @foo() {
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; This function has a loop of SAD pattern. Here we check when VF = 16 the
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; register usage doesn't exceed 16.
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;
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; CHECK-LABEL: foo
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; CHECK: LV(REG): VF = 4
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; CHECK-NEXT: LV(REG): Found max usage: 4
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; CHECK: LV(REG): VF = 8
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; CHECK-NEXT: LV(REG): Found max usage: 7
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; CHECK: LV(REG): VF = 16
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; CHECK-NEXT: LV(REG): Found max usage: 13
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entry:
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br label %for.body
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for.cond.cleanup:
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%add.lcssa = phi i32 [ %add, %for.body ]
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ret i32 %add.lcssa
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for.body:
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%s.015 = phi i32 [ 0, %entry ], [ %add, %for.body ]
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%arrayidx = getelementptr inbounds [1024 x i8], [1024 x i8]* @a, i64 0, i64 %indvars.iv
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%0 = load i8, i8* %arrayidx, align 1
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%conv = zext i8 %0 to i32
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%arrayidx2 = getelementptr inbounds [1024 x i8], [1024 x i8]* @b, i64 0, i64 %indvars.iv
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%1 = load i8, i8* %arrayidx2, align 1
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%conv3 = zext i8 %1 to i32
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%sub = sub nsw i32 %conv, %conv3
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%ispos = icmp sgt i32 %sub, -1
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%neg = sub nsw i32 0, %sub
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%2 = select i1 %ispos, i32 %sub, i32 %neg
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%add = add nsw i32 %2, %s.015
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 1024
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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define i32 @goo() {
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; For indvars.iv used in a computating chain only feeding into getelementptr or cmp,
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; it will not have vector version and the vector register usage will not exceed the
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; available vector register number.
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; CHECK-LABEL: goo
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; CHECK: LV(REG): VF = 4
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; CHECK-NEXT: LV(REG): Found max usage: 4
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; CHECK: LV(REG): VF = 8
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; CHECK-NEXT: LV(REG): Found max usage: 7
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; CHECK: LV(REG): VF = 16
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; CHECK-NEXT: LV(REG): Found max usage: 13
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entry:
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br label %for.body
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for.cond.cleanup: ; preds = %for.body
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%add.lcssa = phi i32 [ %add, %for.body ]
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ret i32 %add.lcssa
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%s.015 = phi i32 [ 0, %entry ], [ %add, %for.body ]
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%tmp1 = add nsw i64 %indvars.iv, 3
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%arrayidx = getelementptr inbounds [1024 x i8], [1024 x i8]* @a, i64 0, i64 %tmp1
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%tmp = load i8, i8* %arrayidx, align 1
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%conv = zext i8 %tmp to i32
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%tmp2 = add nsw i64 %indvars.iv, 2
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%arrayidx2 = getelementptr inbounds [1024 x i8], [1024 x i8]* @b, i64 0, i64 %tmp2
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%tmp3 = load i8, i8* %arrayidx2, align 1
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%conv3 = zext i8 %tmp3 to i32
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%sub = sub nsw i32 %conv, %conv3
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%ispos = icmp sgt i32 %sub, -1
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%neg = sub nsw i32 0, %sub
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%tmp4 = select i1 %ispos, i32 %sub, i32 %neg
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%add = add nsw i32 %tmp4, %s.015
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 1024
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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define i64 @bar(i64* nocapture %a) {
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; CHECK-LABEL: bar
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; CHECK: LV(REG): VF = 2
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; CHECK: LV(REG): Found max usage: 4
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;
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entry:
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br label %for.body
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for.cond.cleanup:
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%add2.lcssa = phi i64 [ %add2, %for.body ]
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ret i64 %add2.lcssa
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for.body:
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%i.012 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
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%s.011 = phi i64 [ 0, %entry ], [ %add2, %for.body ]
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%arrayidx = getelementptr inbounds i64, i64* %a, i64 %i.012
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%0 = load i64, i64* %arrayidx, align 8
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%add = add nsw i64 %0, %i.012
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store i64 %add, i64* %arrayidx, align 8
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%add2 = add nsw i64 %add, %s.011
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%inc = add nuw nsw i64 %i.012, 1
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%exitcond = icmp eq i64 %inc, 1024
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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@d = external global [0 x i64], align 8
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@e = external global [0 x i32], align 4
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@c = external global [0 x i32], align 4
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define void @hoo(i32 %n) {
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; For c[i] = e[d[i]] in the loop, e[d[i]] is not consecutive but its index %tmp can
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; be gathered into a vector. For VF == 16, the vector version of %tmp will be <16 x i64>
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; so the max usage of AVX512 vector register will be 2.
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; AVX512F-LABEL: bar
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; AVX512F: LV(REG): VF = 16
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; AVX512F: LV(REG): Found max usage: 2
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;
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds [0 x i64], [0 x i64]* @d, i64 0, i64 %indvars.iv
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%tmp = load i64, i64* %arrayidx, align 8
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%arrayidx1 = getelementptr inbounds [0 x i32], [0 x i32]* @e, i64 0, i64 %tmp
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%tmp1 = load i32, i32* %arrayidx1, align 4
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%arrayidx3 = getelementptr inbounds [0 x i32], [0 x i32]* @c, i64 0, i64 %indvars.iv
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store i32 %tmp1, i32* %arrayidx3, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 10000
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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}
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