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llvm-project/llvm/test/TableGen
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Florian Hahn 3bc3ec661c [GlobalISel] Only merge memory ops for mayLoad or mayStore instrs. 
Summary:
We only need to merge memory operands for instructions that access
 memory. This slightly reduces the number of actions executed. 

Reviewers: MatzeB, rovka, dsanders

Reviewed By: dsanders

Subscribers: aemerson, igorb, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D36151

llvm-svn: 309944
2017-08-03 14:48:22 +00:00
..
2003-08-03-PassCode.td
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2006-09-18-LargeInt.td
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2010-03-24-PrematureDefaults.td
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AnonDefinitionOnDemand.td
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AsmPredicateCondsEmission.td
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AsmVariant.td
[TableGen] Add a proper namespace to an Instruction in an AsmMatcher test. This is required after r307358.
2017-07-07 05:50:45 +00:00
BitOffsetDecoder.td
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BitsInit.td
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BitsInitOverflow.td
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cast-list-initializer.td
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cast.td
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ClassInstanceValue.td
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CStyleComment.td
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Dag.td
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defmclass.td
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DefmInherit.td
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DefmInsideMultiClass.td
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DuplicateFieldValues.td
[tablegen] Delete duplicates from a vector without skipping elements
2016-12-01 19:38:50 +00:00
eq.td
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eqbit.td
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FieldAccess.td
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foreach.td
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ForeachList.td
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ForeachLoop.td
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ForwardRef.td
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GeneralList.td
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GlobalISelEmitter.td
[GlobalISel] Only merge memory ops for mayLoad or mayStore instrs.
2017-08-03 14:48:22 +00:00
if-empty-list-arg.td
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if.td
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ifbit.td
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Include.inc
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Include.td
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IntBitInit.td
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intrinsic-long-name.td
[MVT][SVE] Scalable vector MVTs (2/3)
2017-04-20 13:36:58 +00:00
intrinsic-varargs.td
[MVT] add v1i1 MVT
2017-05-18 11:29:41 +00:00
LazyChange.td
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LetInsideMultiClasses.td
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lisp.td
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list-element-bitref.td
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ListArgs.td
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ListArgsSimple.td
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listconcat.td
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ListConversion.td
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ListManip.td
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ListOfList.td
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ListSlices.td
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lit.local.cfg
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LoLoL.td
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math.td
TableGen: Add operator !or
2016-11-15 06:49:28 +00:00
MultiClass.td
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MultiClassDefName.td
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MultiClassInherit.td
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MultiPat.td
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nested-comment.td
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NestedForeach.td
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Paste.td
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pr8330.td
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RegisterBankEmitter.td
TableGen: Fix infinite recursion in RegisterBankEmitter
2017-01-30 15:07:01 +00:00
RegisterEncoder.td
[TableGen] Add EncoderMethod to RegisterOperand
2017-05-15 10:13:07 +00:00
SetTheory.td
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SiblingForeach.td
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Slice.td
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strconcat.td
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String.td
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subst2.td
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subst.td
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SuperSubclassSameName.td
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TargetInstrInfo.td
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TargetInstrSpec.td
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TemplateArgRename.td
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Tree.td
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TreeNames.td
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trydecode-emission2.td
tests: accept different TargetOpcode values.
2016-07-07 17:51:42 +00:00
trydecode-emission3.td
tests: accept different TargetOpcode values.
2016-07-07 17:51:42 +00:00
trydecode-emission.td
tests: accept different TargetOpcode values.
2016-07-07 17:51:42 +00:00
TwoLevelName.td
Add test cases that will show the bug that was fixed in r256725.
2016-01-13 07:53:11 +00:00
UnsetBitInit.td
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UnterminatedComment.td
Make shell redirection construct portable
2017-07-12 13:24:46 +00:00
usevalname.td
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ValidIdentifiers.td
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