Files
llvm-project/llvm/lib/CodeGen/MIRParser
Ahmed Bougacha bf480554df [MIRParser] Allow generic register specification on operand.
This completes r292321 by adding support for generic registers, e.g.:

  %2:_(s32) = G_ADD %0, %1

llvm-svn: 292550
2017-01-20 00:29:59 +00:00
..