49e19e906f
and use it in FastISelEmitter.cpp, and make FastISel subtarget aware. Among other things, this lets it work properly on x86 targets that don't have SSE, where it successfully selects x87 instructions. llvm-svn: 55156
333 lines
12 KiB
C++
333 lines
12 KiB
C++
///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of the FastISel class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Instructions.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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/// SelectBinaryOp - Select and emit code for a binary operator instruction,
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/// which has an opcode which directly corresponds to the given ISD opcode.
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///
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bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
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DenseMap<const Value*, unsigned> &ValueMap) {
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MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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unsigned Op0 = ValueMap[I->getOperand(0)];
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if (Op0 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// Check if the second operand is a constant and handle it appropriately.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
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unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
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CI->getZExtValue(), VT.getSimpleVT());
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if (ResultReg == 0)
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// Target-specific code wasn't able to find a machine opcode for
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// the given ISD opcode and type. Halt "fast" selection and bail.
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return false;
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// We successfully emitted code for the given LLVM Instruction.
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ValueMap[I] = ResultReg;
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return true;
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}
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unsigned Op1 = ValueMap[I->getOperand(1)];
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if (Op1 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1);
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if (ResultReg == 0)
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// Target-specific code wasn't able to find a machine opcode for
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// the given ISD opcode and type. Halt "fast" selection and bail.
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return false;
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// We successfully emitted code for the given LLVM Instruction.
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ValueMap[I] = ResultReg;
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return true;
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}
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bool FastISel::SelectGetElementPtr(Instruction *I,
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DenseMap<const Value*, unsigned> &ValueMap) {
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unsigned N = ValueMap[I->getOperand(0)];
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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const Type *Ty = I->getOperand(0)->getType();
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MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
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for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
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OI != E; ++OI) {
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Value *Idx = *OI;
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if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
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unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
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if (Field) {
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// N = N + Offset
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uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
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// FIXME: This can be optimized by combining the add with a
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// subsequent one.
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N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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Ty = StTy->getElementType(Field);
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} else {
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Ty = cast<SequentialType>(Ty)->getElementType();
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// If this is a constant subscript, handle it quickly.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
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if (CI->getZExtValue() == 0) continue;
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uint64_t Offs =
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TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
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N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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continue;
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}
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// N = N + Idx * ElementSize;
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uint64_t ElementSize = TD.getABITypeSize(Ty);
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unsigned IdxN = ValueMap[Idx];
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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// If the index is smaller or larger than intptr_t, truncate or extend
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// it.
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MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
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if (IdxVT.bitsLT(VT))
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IdxN = FastEmit_r(VT, ISD::SIGN_EXTEND, IdxN);
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else if (IdxVT.bitsGT(VT))
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IdxN = FastEmit_r(VT, ISD::TRUNCATE, IdxN);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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if (ElementSize != 1)
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IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
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if (IdxN == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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N = FastEmit_rr(VT, ISD::ADD, N, IdxN);
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if (N == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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}
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// We successfully emitted code for the given LLVM Instruction.
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ValueMap[I] = N;
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return true;
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}
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BasicBlock::iterator
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FastISel::SelectInstructions(BasicBlock::iterator Begin,
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BasicBlock::iterator End,
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DenseMap<const Value*, unsigned> &ValueMap,
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MachineBasicBlock *mbb) {
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MBB = mbb;
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BasicBlock::iterator I = Begin;
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for (; I != End; ++I) {
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switch (I->getOpcode()) {
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case Instruction::Add: {
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ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
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if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
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}
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case Instruction::Sub: {
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ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
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if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
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}
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case Instruction::Mul: {
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ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
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if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
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}
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case Instruction::SDiv:
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if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
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case Instruction::UDiv:
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if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
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case Instruction::FDiv:
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if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
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case Instruction::SRem:
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if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
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case Instruction::URem:
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if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
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case Instruction::FRem:
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if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
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case Instruction::Shl:
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if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
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case Instruction::LShr:
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if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
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case Instruction::AShr:
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if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
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case Instruction::And:
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if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
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case Instruction::Or:
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if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
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case Instruction::Xor:
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if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
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case Instruction::GetElementPtr:
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if (!SelectGetElementPtr(I, ValueMap)) return I;
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break;
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case Instruction::Br: {
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BranchInst *BI = cast<BranchInst>(I);
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// For now, check for and handle just the most trivial case: an
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// unconditional fall-through branch.
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if (BI->isUnconditional()) {
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MachineFunction::iterator NextMBB =
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next(MachineFunction::iterator(MBB));
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if (NextMBB != MF.end() &&
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NextMBB->getBasicBlock() == BI->getSuccessor(0)) {
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MBB->addSuccessor(NextMBB);
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break;
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}
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}
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// Something more complicated. Halt "fast" selection and bail.
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return I;
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}
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default:
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// Unhandled instruction. Halt "fast" selection and bail.
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return I;
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}
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}
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return I;
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}
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FastISel::FastISel(MachineFunction &mf)
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: MF(mf),
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MRI(mf.getRegInfo()),
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TM(mf.getTarget()),
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TD(*TM.getTargetData()),
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TII(*TM.getInstrInfo()),
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TLI(*TM.getTargetLowering()) {
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}
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FastISel::~FastISel() {}
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unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
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return 0;
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}
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unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
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unsigned /*Op0*/) {
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return 0;
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}
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unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
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unsigned /*Op0*/, unsigned /*Op0*/) {
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return 0;
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}
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unsigned FastISel::FastEmit_i(MVT::SimpleValueType, uint64_t /*Imm*/) {
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return 0;
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}
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unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, ISD::NodeType,
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unsigned /*Op0*/, uint64_t /*Imm*/) {
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return 0;
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}
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unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, ISD::NodeType,
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unsigned /*Op0*/, unsigned /*Op1*/,
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uint64_t /*Imm*/) {
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return 0;
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}
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/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
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/// to emit an instruction with an immediate operand using FastEmit_ri.
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/// If that fails, it materializes the immediate into a register and try
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/// FastEmit_rr instead.
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unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
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unsigned Op0, uint64_t Imm,
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MVT::SimpleValueType ImmType) {
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unsigned ResultReg = 0;
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// First check if immediate type is legal. If not, we can't use the ri form.
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if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
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ResultReg = FastEmit_ri(VT, Opcode, Op0, Imm);
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if (ResultReg != 0)
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return ResultReg;
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unsigned MaterialReg = FastEmit_i(ImmType, Imm);
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if (MaterialReg == 0)
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return 0;
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return FastEmit_rr(VT, Opcode, Op0, MaterialReg);
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}
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unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
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return MRI.createVirtualRegister(RC);
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}
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unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
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const TargetRegisterClass* RC) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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BuildMI(MBB, II, ResultReg);
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return ResultReg;
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}
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unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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BuildMI(MBB, II, ResultReg).addReg(Op0);
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return ResultReg;
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}
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unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, unsigned Op1) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
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return ResultReg;
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}
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unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, uint64_t Imm) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
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return ResultReg;
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}
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unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, unsigned Op1, uint64_t Imm) {
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unsigned ResultReg = createResultReg(RC);
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const TargetInstrDesc &II = TII.get(MachineInstOpcode);
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BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
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return ResultReg;
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}
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