74913e1c70
A good portion of this patch is the extra functions that needed to be implemented to support the test case. e.g. storeRegToStackSlot, loadRegFromStackSlot, eliminateFrameIndex. Setting ISD::BR_CC to Expand may appear non-obvious on an architecture with branch+cmp instructions. However, I found it much easier to deal with matching the expanded form. I had to change simm13_lsb0 and simm21_lsb0 to inherit from the Operand<OtherVT> class rather than Operand<i32> in order to keep tablegen happy. This isn't a big deal, but it does seem a shame to lose the uniformity across immediate types when there's not an obvious benefit (I'm hoping a tablegen expert will educate me on what I'm missing here!). Differential Revision: https://reviews.llvm.org/D29935 llvm-svn: 317690
33 lines
1.2 KiB
TableGen
33 lines
1.2 KiB
TableGen
//===-- RISCVCallingConv.td - Calling Conventions RISCV ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the RISCV architecture.
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//
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//===----------------------------------------------------------------------===//
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// RISCV 32-bit C return-value convention.
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def RetCC_RISCV32 : CallingConv<[CCIfType<[i32], CCAssignToReg<[X10, X11]>>]>;
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// RISCV 32-bit C Calling convention.
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def CC_RISCV32 : CallingConv<[
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// Promote i8/i16 args to i32
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CCIfType<[ i8, i16 ], CCPromoteToType<i32>>,
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// All arguments get passed in integer registers if there is space.
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CCIfType<[i32], CCAssignToReg<[ X10, X11, X12, X13, X14, X15, X16, X17]>>,
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// Could be assigned to the stack in 8-byte aligned units, but unsupported
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CCAssignToStack<8, 8>
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]>;
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def CSR : CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
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// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
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def CSR_NoRegs : CalleeSavedRegs<(add)>;
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