57b08b0944
to reflect the new license. These used slightly different spellings that defeated my regular expressions. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351648
85 lines
2.4 KiB
ArmAsm
85 lines
2.4 KiB
ArmAsm
//===----------------------Hexagon builtin routine ------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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.macro FUNCTION_BEGIN name
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.text
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.p2align 5
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.globl \name
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.type \name, @function
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\name:
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.endm
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.macro FUNCTION_END name
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.size \name, . - \name
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.endm
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FUNCTION_BEGIN __hexagon_divdi3
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{
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p2 = tstbit(r1,#31)
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p3 = tstbit(r3,#31)
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}
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{
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r1:0 = abs(r1:0)
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r3:2 = abs(r3:2)
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}
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{
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r6 = cl0(r1:0) // count leading 0's of dividend (numerator)
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r7 = cl0(r3:2) // count leading 0's of divisor (denominator)
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r5:4 = r3:2 // divisor moved into working registers
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r3:2 = r1:0 // dividend is the initial remainder, r3:2 contains remainder
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}
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{
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p3 = xor(p2,p3)
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r10 = sub(r7,r6) // left shift count for bit & divisor
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r1:0 = #0 // initialize quotient to 0
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r15:14 = #1 // initialize bit to 1
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}
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{
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r11 = add(r10,#1) // loop count is 1 more than shift count
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r13:12 = lsl(r5:4,r10) // shift divisor msb into same bit position as dividend msb
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r15:14 = lsl(r15:14,r10) // shift the bit left by same amount as divisor
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}
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{
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p0 = cmp.gtu(r5:4,r3:2) // check if divisor > dividend
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loop0(1f,r11) // register loop
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}
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{
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if (p0) jump .hexagon_divdi3_return // if divisor > dividend, we're done, so return
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}
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.falign
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1:
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{
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p0 = cmp.gtu(r13:12,r3:2) // set predicate reg if shifted divisor > current remainder
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}
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{
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r7:6 = sub(r3:2, r13:12) // subtract shifted divisor from current remainder
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r9:8 = add(r1:0, r15:14) // save current quotient to temp (r9:8)
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}
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{
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r1:0 = vmux(p0, r1:0, r9:8) // choose either current quotient or new quotient (r9:8)
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r3:2 = vmux(p0, r3:2, r7:6) // choose either current remainder or new remainder (r7:6)
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}
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{
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r15:14 = lsr(r15:14, #1) // shift bit right by 1 for next iteration
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r13:12 = lsr(r13:12, #1) // shift "shifted divisor" right by 1 for next iteration
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}:endloop0
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.hexagon_divdi3_return:
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{
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r3:2 = neg(r1:0)
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}
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{
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r1:0 = vmux(p3,r3:2,r1:0)
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jumpr r31
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}
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FUNCTION_END __hexagon_divdi3
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.globl __qdsp_divdi3
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.set __qdsp_divdi3, __hexagon_divdi3
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