Add a bit to mark operands of asm's that conflict

with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.

llvm-svn: 56290

llvm/lib/CodeGen/LiveIntervalAnalysis.cpp

@@ -673,7 +673,10 @@ exit:
 /// registers. for some ordering of the machine instructions [1,N] a
 /// live interval is an interval [i, j) where 1 <= i <= j < N for
 /// which a variable is live
-void LiveIntervals::computeIntervals() {
+void LiveIntervals::computeIntervals() { 
+  AsmsThatEarlyClobber.clear();
+  AsmsWithEarlyClobberConflict.clear();
+
   DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
        << "********** Function: "
        << ((Value*)mf_->getFunction())->getName() << '\n';
@@ -710,8 +713,17 @@ void LiveIntervals::computeIntervals() {
       for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
         MachineOperand &MO = MI->getOperand(i);
         // handle register defs - build intervals
-        if (MO.isRegister() && MO.getReg() && MO.isDef())
+        if (MO.isRegister() && MO.getReg() && MO.isDef()) {
           handleRegisterDef(MBB, MI, MIIndex, MO, i);
+          if (MO.isEarlyClobber()) {
+            AsmsThatEarlyClobber.insert(std::make_pair(MO.getReg(), MI));
+          }
+        }
+        if (MO.isRegister() && !MO.isDef() &&
+            MO.getReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()) &&
+            MO.overlapsEarlyClobber()) {
+          AsmsWithEarlyClobberConflict.insert(std::make_pair(MO.getReg(), MI));
+        }
       }
       
       MIIndex += InstrSlots::NUM;
@@ -740,6 +752,72 @@ bool LiveIntervals::findLiveInMBBs(const LiveRange &LR,
   return ResVal;
 }
 
+/// noEarlyclobberConflict - see whether virtual reg VReg has a conflict with
+/// hard reg HReg because of earlyclobbers.  
+///
+/// Earlyclobber operands may not be assigned the same register as
+/// each other, or as earlyclobber-conflict operands (i.e. those that
+/// are non-earlyclobbered inputs to an asm that also has earlyclobbers).
+///
+/// Thus there are two cases to check for:
+/// 1.  VReg is an earlyclobber-conflict register and HReg is an earlyclobber
+/// register in some asm that also has VReg as an input.
+/// 2.  VReg is an earlyclobber register and HReg is an earlyclobber-conflict
+/// input elsewhere in some asm.
+/// In both cases HReg can be assigned by the user, or assigned early in
+/// register allocation.
+/// 
+/// Dropping the distinction between earlyclobber and earlyclobber-conflict,
+/// keeping only one multimap, looks promising, but two earlyclobber-conflict
+/// operands may be assigned the same register if they happen to contain the 
+/// same value, and that implementation would prevent this.
+///
+bool LiveIntervals::noEarlyclobberConflict(unsigned VReg, VirtRegMap &vrm,
+                                           unsigned HReg) {
+  typedef std::multimap<unsigned, MachineInstr*>::iterator It;
+
+  // Short circuit the most common case.
+  if (AsmsWithEarlyClobberConflict.size()!=0) {
+    std::pair<It, It> x = AsmsWithEarlyClobberConflict.equal_range(VReg);
+    for (It I = x.first; I!=x.second; I++) {
+      MachineInstr* MI = I->second;
+      for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
+        MachineOperand &MO = MI->getOperand(i);
+        if (MO.isRegister() && MO.isEarlyClobber()) {
+          unsigned PhysReg = MO.getReg();
+          if (PhysReg && TargetRegisterInfo::isVirtualRegister(PhysReg)) {
+            if (!vrm.hasPhys(PhysReg))
+              continue;
+            PhysReg = vrm.getPhys(PhysReg);
+          }
+          if (PhysReg==HReg)
+            return false;
+        }
+      }
+    }
+  }
+  // Short circuit the most common case.
+  if (AsmsThatEarlyClobber.size()!=0) {
+    std::pair<It, It> x = AsmsThatEarlyClobber.equal_range(VReg);
+    for (It I = x.first; I!=x.second; I++) {
+      MachineInstr* MI = I->second;
+      for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
+        MachineOperand &MO = MI->getOperand(i);
+        if (MO.isRegister() && MO.overlapsEarlyClobber()) {
+          unsigned PhysReg = MO.getReg();
+          if (PhysReg && TargetRegisterInfo::isVirtualRegister(PhysReg)) {
+            if (!vrm.hasPhys(PhysReg))
+              continue;
+            PhysReg = vrm.getPhys(PhysReg);
+          }
+          if (PhysReg==HReg)
+            return false;
+        }
+      }
+    }
+  }
+  return true;
+}
 
 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
   float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?