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Fix whitespace, 80-column violations, embedded tabs for the

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TargetInfo class.

llvm-svn: 249872
This commit is contained in:
Eric Christopher
2015-10-09 18:39:59 +00:00
parent 8c47b427f9
commit b093d69062
3 changed files with 36 additions and 31 deletions
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14
clang/include/clang/Basic/TargetInfo.h
View File

@@ -108,9 +108,9 @@ public:
virtual ~TargetInfo();
/// \brief Retrieve the target options.
TargetOptions &getTargetOpts() const {
TargetOptions &getTargetOpts() const {
assert(TargetOpts && "Missing target options");
return *TargetOpts;
return *TargetOpts;
}
///===---- Target Data Type Query Methods -------------------------------===//
@@ -316,7 +316,9 @@ public:
unsigned getLongLongAlign() const { return LongLongAlign; }
/// \brief Determine whether the __int128 type is supported on this target.
virtual bool hasInt128Type() const { return getPointerWidth(0) >= 64; } // FIXME
virtual bool hasInt128Type() const {
return getPointerWidth(0) >= 64;
} // FIXME
/// \brief Return the alignment that is suitable for storing any
/// object with a fundamental alignment requirement.
@@ -632,7 +634,7 @@ public:
}
/// \brief Indicate that this is an input operand that is tied to
/// the specified output operand.
/// the specified output operand.
///
/// Copy over the various constraint information from the output.
void setTiedOperand(unsigned N, ConstraintInfo &Output) {
@@ -814,7 +816,7 @@ public:
// \brief Validate the contents of the __builtin_cpu_supports(const char*)
// argument.
virtual bool validateCpuSupports(StringRef Name) const { return false; }
// \brief Returns maximal number of args passed in registers.
unsigned getRegParmMax() const {
assert(RegParmMax < 7 && "RegParmMax value is larger than AST can handle");
@@ -898,7 +900,7 @@ public:
};
/// \brief Determines whether a given calling convention is valid for the
/// target. A calling convention can either be accepted, produce a warning
/// target. A calling convention can either be accepted, produce a warning
/// and be substituted with the default calling convention, or (someday)
/// produce an error (such as using thiscall on a non-instance function).
virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {

20
clang/lib/Basic/TargetInfo.cpp
View File

@@ -287,9 +287,9 @@ void TargetInfo::adjust(const LangOptions &Opts) {
LongLongWidth = LongLongAlign = 128;
HalfWidth = HalfAlign = 16;
FloatWidth = FloatAlign = 32;
// Embedded 32-bit targets (OpenCL EP) might have double C type
// defined as float. Let's not override this as it might lead
// Embedded 32-bit targets (OpenCL EP) might have double C type
// defined as float. Let's not override this as it might lead
// to generating illegal code that uses 64bit doubles.
if (DoubleWidth != FloatWidth) {
DoubleWidth = DoubleAlign = 64;
@@ -339,7 +339,7 @@ static StringRef removeGCCRegisterPrefix(StringRef Name) {
/// Sema.
bool TargetInfo::isValidClobber(StringRef Name) const {
return (isValidGCCRegisterName(Name) ||
Name == "memory" || Name == "cc");
Name == "memory" || Name == "cc");
}
/// isValidGCCRegisterName - Returns whether the passed in string
@@ -379,11 +379,11 @@ bool TargetInfo::isValidGCCRegisterName(StringRef Name) const {
for (unsigned i = 0; i < NumAddlNames; i++)
for (unsigned j = 0; j < llvm::array_lengthof(AddlNames[i].Names); j++) {
if (!AddlNames[i].Names[j])
break;
break;
// Make sure the register that the additional name is for is within
// the bounds of the register names from above.
if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames)
return true;
return true;
}
// Now check aliases.
@@ -432,11 +432,11 @@ TargetInfo::getNormalizedGCCRegisterName(StringRef Name) const {
for (unsigned i = 0; i < NumAddlNames; i++)
for (unsigned j = 0; j < llvm::array_lengthof(AddlNames[i].Names); j++) {
if (!AddlNames[i].Names[j])
break;
break;
// Make sure the register that the additional name is for is within
// the bounds of the register names from above.
if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames)
return Name;
return Name;
}
// Now check aliases.
@@ -578,7 +578,7 @@ bool TargetInfo::validateInputConstraint(ConstraintInfo *OutputConstraints,
if (OutputConstraints[i].isReadWrite())
return false;
// If the constraint is already tied, it must be tied to the
// If the constraint is already tied, it must be tied to the
// same operand referenced to by the number.
if (Info.hasTiedOperand() && Info.getTiedOperand() != i)
return false;
@@ -598,7 +598,7 @@ bool TargetInfo::validateInputConstraint(ConstraintInfo *OutputConstraints,
if (!resolveSymbolicName(Name, OutputConstraints, NumOutputs, Index))
return false;
// If the constraint is already tied, it must be tied to the
// If the constraint is already tied, it must be tied to the
// same operand referenced to by the number.
if (Info.hasTiedOperand() && Info.getTiedOperand() != Index)
return false;

33
clang/lib/Basic/Targets.cpp
View File

@@ -3717,9 +3717,9 @@ public:
};
static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
// Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports
// __declspec natively under -fms-extensions, but we define a no-op __declspec
// macro anyway for pre-processor compatibility.
// Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
// supports __declspec natively under -fms-extensions, but we define a no-op
// __declspec macro anyway for pre-processor compatibility.
if (Opts.MicrosoftExt)
Builder.defineMacro("__declspec", "__declspec");
else
@@ -4260,12 +4260,12 @@ class ARMTargetInfo : public TargetInfo {
}
void setAtomic() {
// when triple does not specify a sub arch,
// when triple does not specify a sub arch,
// then we are not using inline atomics
bool ShouldUseInlineAtomic =
(ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
(ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
// Cortex M does not support 8 byte atomics, while general Thumb2 does.
// Cortex M does not support 8 byte atomics, while general Thumb2 does.
if (ArchProfile == llvm::ARM::PK_M) {
MaxAtomicPromoteWidth = 32;
if (ShouldUseInlineAtomic)
@@ -4275,7 +4275,7 @@ class ARMTargetInfo : public TargetInfo {
MaxAtomicPromoteWidth = 64;
if (ShouldUseInlineAtomic)
MaxAtomicInlineWidth = 64;
}
}
}
bool isThumb() const {
@@ -4446,7 +4446,7 @@ public:
for (const char *Feature : TargetFeatures)
if (Feature[0] == '+')
Features[Feature+1] = true;
Features[Feature+1] = true;
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
@@ -4620,17 +4620,17 @@ public:
Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
// ACLE 6.4.3 Unaligned access supported in hardware
if (Unaligned)
if (Unaligned)
Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
// ACLE 6.4.4 LDREX/STREX
if (LDREX)
Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
// ACLE 6.4.5 CLZ
if (ArchVersion == 5 ||
(ArchVersion == 6 && CPUProfile != "M") ||
ArchVersion > 6)
if (ArchVersion == 5 ||
(ArchVersion == 6 && CPUProfile != "M") ||
ArchVersion > 6)
Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
// ACLE 6.5.1 Hardware Floating Point
@@ -4685,7 +4685,8 @@ public:
Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
// ACLE 6.4.10 Hardware Integer Divide
if (((HWDiv & HWDivThumb) && isThumb()) || ((HWDiv & HWDivARM) && !isThumb())) {
if (((HWDiv & HWDivThumb) && isThumb()) ||
((HWDiv & HWDivARM) && !isThumb())) {
Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
}
@@ -4712,7 +4713,8 @@ public:
Builder.defineMacro("__ARM_NEON__");
// current AArch32 NEON implementations do not support double-precision
// floating-point even when it is present in VFP.
Builder.defineMacro("__ARM_NEON_FP", "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
Builder.defineMacro("__ARM_NEON_FP",
"0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
}
Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
@@ -5879,7 +5881,8 @@ class SystemZTargetInfo : public TargetInfo {
public:
SystemZTargetInfo(const llvm::Triple &Triple)
: TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) {
: TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
HasVector(false) {
IntMaxType = SignedLong;
Int64Type = SignedLong;
TLSSupported = true;