From a9da1de5f46691284d2bb7973e44c6b34b8c2bc5 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Fri, 9 Nov 2018 14:35:44 +0000 Subject: [PATCH] [RISCV] Update test/CodeGen/RISCV/calling-conv.ll after rL346432 The DAGCombiner changes led to a different schedule. llvm-svn: 346496 --- llvm/test/CodeGen/RISCV/calling-conv.ll | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/calling-conv.ll b/llvm/test/CodeGen/RISCV/calling-conv.ll index 8440045fd91a..7d93499ab1d2 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv.ll @@ -997,14 +997,14 @@ define void @caller_large_scalar_ret() nounwind { define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind { ; RV32I-FPELIM-LABEL: callee_large_struct_ret: ; RV32I-FPELIM: # %bb.0: +; RV32I-FPELIM-NEXT: addi a1, zero, 4 +; RV32I-FPELIM-NEXT: sw a1, 12(a0) +; RV32I-FPELIM-NEXT: addi a1, zero, 3 +; RV32I-FPELIM-NEXT: sw a1, 8(a0) ; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: sw a1, 4(a0) ; RV32I-FPELIM-NEXT: addi a1, zero, 1 ; RV32I-FPELIM-NEXT: sw a1, 0(a0) -; RV32I-FPELIM-NEXT: addi a1, zero, 3 -; RV32I-FPELIM-NEXT: sw a1, 8(a0) -; RV32I-FPELIM-NEXT: addi a1, zero, 4 -; RV32I-FPELIM-NEXT: sw a1, 12(a0) ; RV32I-FPELIM-NEXT: ret ; ; RV32I-WITHFP-LABEL: callee_large_struct_ret: @@ -1013,14 +1013,14 @@ define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) no ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 +; RV32I-WITHFP-NEXT: addi a1, zero, 4 +; RV32I-WITHFP-NEXT: sw a1, 12(a0) +; RV32I-WITHFP-NEXT: addi a1, zero, 3 +; RV32I-WITHFP-NEXT: sw a1, 8(a0) ; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: sw a1, 4(a0) ; RV32I-WITHFP-NEXT: addi a1, zero, 1 ; RV32I-WITHFP-NEXT: sw a1, 0(a0) -; RV32I-WITHFP-NEXT: addi a1, zero, 3 -; RV32I-WITHFP-NEXT: sw a1, 8(a0) -; RV32I-WITHFP-NEXT: addi a1, zero, 4 -; RV32I-WITHFP-NEXT: sw a1, 12(a0) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 16