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Split the Add, Sub, and Mul instruction opcodes into separate

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integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897
This commit is contained in:
Dan Gohman
2009-06-04 22:49:04 +00:00
parent 72a4d2fec1
commit a5b9645c4b
265 changed files with 2374 additions and 1924 deletions
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9
llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
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@@ -77,9 +77,12 @@ static unsigned GetEncodedCastOpcode(unsigned Opcode) {
static unsigned GetEncodedBinaryOpcode(unsigned Opcode) {
switch (Opcode) {
default: assert(0 && "Unknown binary instruction!");
case Instruction::Add: return bitc::BINOP_ADD;
case Instruction::Sub: return bitc::BINOP_SUB;
case Instruction::Mul: return bitc::BINOP_MUL;
case Instruction::Add:
case Instruction::FAdd: return bitc::BINOP_ADD;
case Instruction::Sub:
case Instruction::FSub: return bitc::BINOP_SUB;
case Instruction::Mul:
case Instruction::FMul: return bitc::BINOP_MUL;
case Instruction::UDiv: return bitc::BINOP_UDIV;
case Instruction::FDiv:
case Instruction::SDiv: return bitc::BINOP_SDIV;