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Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When

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set, these flags indicate the instructions source / def operands have special
register allocation requirement that are not captured in their register classes.
Post-allocation passes (e.g. post-alloc scheduler) should not change their
allocations. e.g. ARM::LDRD require the two definitions to be allocated
even / odd register pair.

llvm-svn: 83196
This commit is contained in:
Evan Cheng
2009-10-01 08:21:18 +00:00
parent e364e7bc2b
commit 46668e09be
5 changed files with 31 additions and 1 deletions
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2
llvm/utils/TableGen/CodeGenInstruction.cpp
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@@ -101,6 +101,8 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
mayHaveSideEffects = R->getValueAsBit("mayHaveSideEffects");
neverHasSideEffects = R->getValueAsBit("neverHasSideEffects");
isAsCheapAsAMove = R->getValueAsBit("isAsCheapAsAMove");
hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq");
hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq");
hasOptionalDef = false;
isVariadic = false;