Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
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@@ -395,9 +395,10 @@ static MachineBasicBlock *findFalseBlock(MachineBasicBlock *BB,
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/// ReverseBranchCondition - Reverse the condition of the end of the block
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/// branch. Swap block's 'true' and 'false' successors.
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bool IfConverter::ReverseBranchCondition(BBInfo &BBI) {
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DebugLoc dl; // FIXME: this is nowhere
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if (!TII->ReverseBranchCondition(BBI.BrCond)) {
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TII->RemoveBranch(*BBI.BB);
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TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond);
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TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl);
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std::swap(BBI.TrueBB, BBI.FalseBB);
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return true;
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}
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@@ -862,8 +863,9 @@ void IfConverter::InvalidatePreds(MachineBasicBlock *BB) {
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///
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static void InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB,
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const TargetInstrInfo *TII) {
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DebugLoc dl; // FIXME: this is nowhere
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SmallVector<MachineOperand, 0> NoCond;
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TII->InsertBranch(*BB, ToBB, NULL, NoCond);
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TII->InsertBranch(*BB, ToBB, NULL, NoCond, dl);
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}
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/// RemoveExtraEdges - Remove true / false edges if either / both are no longer
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@@ -1014,6 +1016,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
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BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()];
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BBInfo *CvtBBI = &TrueBBI;
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BBInfo *NextBBI = &FalseBBI;
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DebugLoc dl; // FIXME: this is nowhere
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SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
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if (Kind == ICTriangleFalse || Kind == ICTriangleFRev)
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@@ -1078,7 +1081,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
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CvtBBI->BrCond.end());
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if (TII->ReverseBranchCondition(RevCond))
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assert(false && "Unable to reverse branch condition!");
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TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond);
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TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond, dl);
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BBI.BB->addSuccessor(CvtBBI->FalseBB);
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}
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